A configuration of a conventional information processing apparatus in which a plurality of components are included in one casing is depicted in FIG. 16. An information processing apparatus 300 includes, inside a casing, hardware components SB (System Board) 303A, SB 303B, SB 303C, and SB 303D (sometimes collectively referred to as “SB 303”) each capable of starting-up an OS, a power controller 302 for controlling a power source of the SB 303, and a resident power source 301.
The power controller 302 has a voltage margin control function of changing voltage to be supplied to the SB 303. An operator executing a voltage margin test uses an external terminal 400 connected to the power controller 302 to execute the voltage margin test which is a test of changing voltage to be supplied to the SB 303. The voltage margin denotes an allowable range of a voltage variation with respect to a prescribed voltage value, and voltage margin test is a test of measuring a voltage variation with respect to a prescribed voltage value that a target apparatus allows.
The components in the information processing apparatus 300 will be described.
Each SB in the SB 303 is constituted by a CPU (Central Processing Unit), a memory, an HDD (Hard Disk Drive), a PCI (Peripheral Component Interconnect) card, and the like. Each SB in the SB 303 is a hardware component functioning as one calculator and is capable of starting-up an OS.
The power controller 302 is a mechanism that operates with a power supply from the resident power source 301 and manages a power source of hardware in the information processing apparatus 300. The power controller 302 is constituted by a unique CPU and memory independent of those provided in the SB 303, an external interface, an ROM (Read Only Memory) for storing firmware, and the like. The power controller 302 has a function of controlling connection/disconnection of a power source to/from each SB in the SB 303 individually so as to provide a function such as a serial interface, LAN, or the like. The function of the power controller 302 is achieved by firmware stored in the ROM and hardware resource such as the CPU and memory cooperating each other. Hereinafter, the firmware of the power controller 302 is referred to as “power control firmware” as needed.
The resident power source 301 supplies power to hardware provided in the information processing apparatus 300. The resident power source 301 constantly supplies power to the power controller 302, while it supplies power to the SB 303 under the control of the power controller 302.
The external terminal 400 is a terminal connected to the power controller 302 by a serial interface or LAN interface and receives a power control instruction from an operator. The information processing apparatus 300 receives an instruction such as activation or stop of a power source through a serial connection terminal software operating under the control of the external terminal 400.
A configuration of a hardware component of the SB 303, which is a target of the voltage margin test, concerning a power supply is depicted in FIG. 17. While the SB 303A is taken as an example in FIG. 17, the same configuration may be used for other SBs.
A DDC (DC/DC Converter) for controlling voltage required for the respective components such as the CPU (Central Processing Unit), memory and LSI (Large Scale Integrated circuit) provided in the hardware component exists in the SB 303A. The DDC receives TRIM input as a trim for an output voltage value and thereby can change the output voltage value. The power control firmware controls respective DDC and a DAC (Digital-to-Analog Converter).
A configuration of a conventional power control firmware provided in the power controller 302 is depicted in FIG. 18.
A power control firmware 302 includes a hardware interface section 323 for controlling an interface with hardware in the information processing apparatus 300, a control section 322 for performing control so as to allow respective functions of the hardware interface section 323 to operate in association with each other, and a serial/CLI (Command Line Interface) section 321 for providing the function of the control section 322 to a user.
The hardware interface section 323 has a function of setting a voltage margin value in the hardware. Further, the hardware interface section 323 provides a Write/Read function of a hardware setting value to/from the DDC, which is required for setting/control of the voltage margin value, to other components in the power control firmware.
The control section 322 realizes a series of processing steps for power control by using functional operation processing performed in the hardware interface section 323. When a power-on instruction is issued, the control section 322 performs a series of control processing steps called power-on sequence, including power-on of the each DDC in the SB 303, initialization of each hardware, and activation of the CPU. Further, in the power-on sequence, the control section 322 performs predetermined functional operation processing (Set_Voltage_margin function, in the case of an example of FIG. 18) in the hardware interface section 323 for a DDC to which a voltage margin setting instruction is instructed. In this case, the control section 322 performs voltage margin control at the time of the power-on sequence in time with power-on control for each DDC.
The serial/CLI section 321 provides to an operator the power-on/off function of the control section 322 as a CLI through the serial interface and terminal software in the external terminal 400.
A specification example on the CLI for a specific system board is depicted. First, a specification example of power-on/off for a specific system board is as follows:                Power_On/Power_Off [SB name]        
The serial/CLI section 321 provides a voltage margin control function that the control section 322 performs in the power-on sequence to an operator of the voltage margin test as the CLI. A specification example in which voltage margins set in all the DDCs on the SB specified at the power-on time are increased is as follows:                Set_Voltage_margin [SB name]_all+[margin (%)] A specification example in which voltage margins set in all the DDCs on the SB specified at the power-on time are decreased is as follows:        Set_Voltage_margin [SB name]_all−[margin (%)] A specification example in which a voltage margin set in the specified DDC on the SB specified at the power-on time is increased is as follows:        Set_Voltage_margin [SB name]_[DDC name]+[margin (%)] A specification example in which a voltage margin set in the specified DDC on the SB specified at the power-on time is decreased is as follows:        Set_Voltage_margin [SB name]_[DDC name]−[margin (%)]        
The serial/CLI section 321 can also receive a waiting instruction. When receiving the stand-by instruction, the serial/CLI section 321 waits with doing nothing for a specified waiting time. A specification example of the waiting instruction is as follows:                wait [waiting time] minute        
Processing steps of a conventional voltage margin test will be described with reference to a flowchart of FIG. 19.
An operator uses the CLI of the external terminal 400 to issue a voltage margin setting instruction (S101), and issues an instruction of powering on a target SB at a test voltage value (voltage value obtained by increasing (or decreasing) a prescribed voltage value by a voltage margin (%)) (S102). The operator executes the test according to a test program operating under an OS which operates in the test target (SB) powered on at the test voltage value (S103).
After completion of the test at the test voltage value, the test target (SB) is powered off based on an instruction from the CLI (S104). In the case where there is another test voltage value (Yes in S105), a series of the above processing steps including the voltage margin setting instruction (S101), power-on (S102), execution of test (S103), and power-off (S104) are executed once again.
As described above, at the time of execution of the conventional voltage margin test, the SB which is a test target needs to be powered on/off every time a setting value of the voltage margin test is changed.
As a prior art relating to the present invention, there is known a service processor disclosed in Japanese Laid-Open Patent Publication No. 05-307462. The service processor can reduce the number of times of key input by using a pattern setting method to thereby simplifying input operation and reducing input error, and thereby increasing time efficiency. Further, there is known a voltage control method and a voltage control circuit disclosed in Japanese Laid-Open Patent Publication No. 2004-184111. The voltage control method and voltage control circuit can reduce man-hours required for inspection and eliminate the possibility of supplying an excessive voltage to damage a device.
[Patent Document 1]
Japanese Laid-Open Patent Publication No. 5-307492
[Patent Document 2]
Japanese Laid-Open Patent Publication No. 2004-184111
The following problems exist in the voltage margin test in which an instruction of power-on/off is issued every time the operator changes the margin setting value.
The voltage margin is set at the time of power-on sequence, so that it is preferably to power-on/off operation for each margin setting, thus taking much time in completing the test. Further, when a configuration in which the voltage margin can be changed in a power-on state is adopted in order to cope with the above problem, unexpected hardware malfunction may occur due to a rapid change in the voltage value.
In order to cope with the abovementioned unexpected hardware malfunction, there can be considered a method in which a function capable of quickly setting an intended voltage value in a power-on state while avoiding a rapid change in the voltage value is implemented in the power controller 302 as a function of the firmware can be considered. However, this involves development cost, man-hours, and time. Similarly, when hardware is constructed so as to endure a rapid change in the voltage value during a power-on state, the system becomes expensive.